1. Field of the Invention
The present invention relates to a test system for use in an asynchronous transmission mode (ATM) system, and more specifically to a test system for checking the integrity of data transmitted in ATM cells and for testing a switching unit by transmitting a test cell having an optional band.
2. Description of the Related Art
In an ATM, data can be processed at a low speed of several kbps through digital telephone, etc., and at a high speed of several hundred Mbps in the transmission of dynamic image data.
In the ATM, data are segmented for a fixed length of 48 bytes, and transmitted with 5-byte control information referred to as a header. The 53-byte information block is referred to as a cell. Since the ATM cell is fixed in length, detecting a header position also detects succeeding header information and information to be transmitted.
In the ATM, cells are transmitted at predetermined intervals. If data are transmitted at a high speed, the number of significant cells transmitted per unit time is increased, whereas in a low speed transmission, the number of significant cells transmitted per unit time is decreased by issuing idle cells when significant cells are not transmitted. An idle cell can be identified through a specific header pattern. In a network, the idle cells are discarded when user data are multiplexed so that only significant cells can be extracted. Thus, significant cells can be transmitted at an optional speed in the ATM.
FIG. 1 shows a rough configuration of the ATM system containing an ATM switching unit. In FIG. 1, if subscriber A transmits data to subscriber B, an ATM cell outputted by subscriber A is transmitted as an optical signal via an optical fiber line, converted to an electric signal by an optic-electrical converting unit 1, and applied to a cell synchronizing unit 2.
The cell synchronizing unit 2 synchronizes cells and generates a pulse signal indicating the timing of the heading cell. A header error control (HEC) checks for errors in the contents in the header of a cell.
Once the cells have been synchronized by the cell synchronizing unit 2, they can be processed individually, and each of the cells is applied to a switch 5 through a subscriber interface 3 and a multiplexer 4. The switch 5 switches the cells in a route according to the control information in the header of a cell, and applies them to subscriber B.
The cells outputted from the switch 5 are applied to an electro-optical converting unit 14 through a demultiplexer 11, subscriber interface 12, and synchronization signal providing unit 13.
The above described ATM system performs a serial/parallel conversion in the cell synchronizing unit 2, and transmits data in cells in, for example, a parallel 8-bit format. Thus, a parallel/serial conversion is performed by the synchronization signal providing unit 13, and the data are transmitted as optical signals in a serial format again.
Various tests are conducted to confirm the operation of the above described ATM system. For example, conducted is a test of determining whether or not data are destroyed in the ATM system. In this case, a parity bit provided by an input unit for 8-bit data is checked in an output unit in the above described ATM system so as to determine whether or not each of the 8-bit data transmitted in an 8-bit parallel format is normal and the entire transmission data are normal without any problems.
However, in the method of searching a parity bit for an error, although an error can be detected when an odd number of errors have arisen in 8-bit data, it cannot be detected when an even number of errors have arisen. An ATM cell is provided with switching information in an ATM switch based on a virtual path identifier (VPI) and a virtual channel identifier (VCI) stored in a header, and data are routed in the ATM switch based on the switching information. Accordingly, when a part of the above mentioned identifiers contain an even number of error bits, the cell cannot be routed correctly, but the errors cannot be detected by a maintenance system. Likewise, errors may not be detected even if user information data have been destroyed.
Thus, in the method of searching a parity bit for an error, it is not certain whether or not data have been normally transmitted in the ATM system. Furthermore, the method has the problem that a parity information transmission signal line is required in addition to a data transmission signal line.
Another method commonly used for testing the ATM system is operated by generating a test cell in a trunk (not shown in the attached drawings) provided, for example, in a stage prior to the multiplexer 4, and transmitting the test cell to the switch 5. This test is conducted normally to check the route in the switch 5 by transmitting a test cell from a trunk to the switch 5 at predetermined intervals at an instruction of a software interface connected to the trunk and determining whether or not the test cell has passed through a correct route in the switch 5.
However, the above described test is insufficient for an ATM system. That is, since the ATM switching unit processes data of various bands, a load test should be conducted using a test cell having a band of actual transmission data. For example, based on an assumption that data are transmitted at a rate of 1.5 Mbps and a test cell having a band of 1.5 Mbps is transmitted, a test of checking the state of a buffer in the switch 5 and a test of checking the existence of a discarded cell due to congestion of cells must be conducted.
To conduct such load tests, the number of generated test cells per unit time, that is, bands of test cells, should be variable and test cells of various bands should be generated. Conventionally, there have been no units for generating test cells of various bands. Accordingly, a terminal unit, etc. having a desired band is connected each time it is required, or an external measure, etc. must be connected for this kind of test.